The present invention relates to a system for addressing memory packs within a microprocessor system.
Microprocessor systems are widely used in many kinds of electronic apparatus such as personal computers, electronic measurement instruments, etc. A microprocessor system usually includes a microprocessor as a central processing unit (CPU), a read only memory (ROM) for storing microprograms and a random access memory (RAM) for temporary memory storage. The CPU processes data (or sometimes executes programs in the RAM) in accordance with the microprograms stored in the ROM. Sometimes, it is desirable to change the microcode in the ROM, to reconfigure, or to expand the memory capacity of the RAM for changing or improving the function of the microprocessor system. For this end, a memory pack system to configure memory space is useful. The memory pack may include a ROM storing another operating system microprogram instead of the ROM originally in the microprocessor system, or the pack may simply include a RAM for increasing the memory storage capacity.
FIG. 1 illustrates a conventional apparatus employing a microprocessor system which can accept a memory pack. As described hereinbefore, microprocessor system (processor) 10 includes CPU 12, ROM 14 and RAM 16 which are connected to main bus 18 which includes the appropriate data, address and control lines consistent with the specific CPU chosen. CPU 12 may be an eight-bit microprocessor such as the 8080, the Z-80A or the like, in which case the address bus would consist of sixteen lines. In addition, processor 10 further includes keyboard 20 as an input device connected to bus 18, and clock generator 22 for applying a clock signal to each system component. Instrument 24, which could be any piece of electronic instrumentation, e.g. a logic state analyzer, may be connected to bus 18 for control by CPU 12. Processor 10 can accept memory pack 26 and further to that purpose processor 10 has data connector 28, address connector 30 for address lines A0 through A12, and control connector 32, wherein these connectors 28, 30, and 32 are connected to bus 18. In this instance, the memory capacity of memory pack 26 must be less than 8K bit (8K-byte), since address connector 30 has thirteen contacts.
Memory pack 26 includes four 2K-bit (or 2K-byte) memory chips 34 through 40 and decoder 42. The memory chips may be RAM or ROM integrated circuits (ICs). The output signals from memory chips 34 through 40 are coupled to data connector 28, and the address signals are connected to lines A0 through A10 of address connector 30. Lines A11 and A12 are connected to input terminals A and B of decoder 42 and the outputs (0, 1, 2, 3) thereof are connected to the enable terminals E of memory chips 34 through 40. Decoder 42 is enabled in accordance with a pack select signal applied from bus 18 via control connector 32 to the enable terminal E. Decoder 42 acts as a selector for selecting one of memory chips 34 through 40. If the memory chips are RAMS, a read/write control line is also needed.
This conventional apparatus can change the ROMs or increase the RAMS, however, memory pack 26 is cumbersome in size because it includes many IC chips. If the memory pack size is large, it is not only burdensome to carry the additional memory packs but the system must provide a correspondingly large space to accept the memory packs.